The present invention relates generally to a metastable tolerant asynchronous interface circuit, and more particularly to a device for passing data from a circuit running at a first clock rate to another circuit running at a second clock rate.
One problem associated with passing data from a circuit running at one clock rate to another circuit running at a different clock rate is that signals from the one circuit to flip-flops in the other circuit will sometimes change at the flip-flop input while the clock is trying to load that flip-flop. When this happens the flip-flop may end up getting a solid logic 0, a solid logic 1, or something in between, called a metastable state. Since the metastable state is not a reliable logic 0 or 1, the circuitry that it drives can become confused and produce spurious outputs.
United States patents of interest include U.S. Pat. No. 4,289,979, to Muller, which teaches a master-slave flip-flop circuit. U.S. Pat. No. 4,495,628 to Zasio also teaches a master-slave latching circuit, having delay testing capability. U.S. Pat. No. 4,698,830 to Barzilai et al teaches a shift register latch circuit having two clocked DC latches. U.S. Pat. No. 4,780,895 to Paul teaches a circuit for stabilizing the pulse output from two counters.